A temperature-dependent refresh circuit configured to increase or decrease a count value of a refresh timer according to a self-refresh signal

ABSTRACT

Systems and apparatuses for memory devices utilizing a continuous self-refresh timer are provided. An example apparatus includes a self-refresh timer configured to generate a signal periodically, wherein a period of the signal is based on a self-refresh refresh time interval, wherein the self-refresh refresh time interval is dependent on temperature information. The apparatus may further include a memory bank comprising at least a first subarray and in communication with a first subarray refresh circuit, which may include a first refresh status counter. The first refresh status counter may be in communication with the self-refresh timer and configured to receive the signal from the self-refresh timer, change a count value of the first refresh status counter in a first direction each time the signal is received, and change the count value of the first refresh status counter in a second direction each time the first subarray is refreshed.

BACKGROUND

The basic operations for dynamic random access memory (DRAM) includereading data, writing data, and refreshing of stored data. Modern DRAMcells must be refreshed periodically to prevent the loss or corruptionof data stored by the memory cells, typically through leakage in thememory cells. Conventionally, periodic refreshes are performed on anentire rank, or alternatively on an entire bank in per-bank refreshoperations. Thus, while being refreshed, either the entire rank, or theentire bank, is prevented from handling requests.

Self-refresh is a technique for DRAM refresh without requiring a memorycontroller to provide refresh commands. Typically, while in self-refreshmode, a self-refresh timer determines when a refresh is needed based ontemperature information. When self-refresh mode is entered, theself-refresh timer starts from 0, and when self-refresh mode is exited,the self-refresh timer is reset. Because the status of refreshes isunknown when self-refresh mode is entered, a refresh is triggered uponeach entry into self-refresh mode. This can lead to excess powerconsumption by unnecessary refresh operations when self-refresh mode isentered and exited in quick succession.

BRIEF DESCRIPTION OF THE DRAWINGS

A further understanding of the nature and advantages of particularembodiments may be realized by reference to the remaining portions ofthe specification and the drawings, in which like reference numerals areused to refer to similar components. In some instances, a sub-label isassociated with a reference numeral to denote one of multiple similarcomponents. When reference is made to a reference numeral withoutspecification to an existing sub-label, it is intended to refer to allsuch multiple similar components.

FIG. 1A is a schematic block diagram of a memory device configured forpower saving self-refresh, in accordance with various embodiments.

FIG. 1B is a schematic block diagram of a memory device furtherconfigured for subarray parallel refresh, in accordance with variousembodiments.

FIG. 1C is a schematic block diagram of an alternative architecture fora memory device configured for subarray parallel refresh, in accordancewith various embodiments

FIG. 2 is a schematic diagram of a refresh control circuit, inaccordance with various embodiments.

FIG. 3 is a timing diagram showing self-refresh operation, in accordancewith various embodiments.

FIG. 4 is a timing diagram showing subarray parallel refresh operation,in accordance with various embodiments.

FIG. 5A is allow diagram of a process for setting a refresh flag basedon a self-refresh refresh time interval, in accordance with variousembodiments.

FIG. 5B is a flow diagram of a process for self-refresh of a memorydevice, in accordance with various embodiments.

FIG. 6A is a flow diagram of a process for refresh status counteroperation based on the self-refresh refresh time interval, in accordancewith various embodiments.

FIG. 6B is a flow diagram for subarray parallel refresh of a memorydevice, in accordance with various embodiments.

FIG. 7 is a block diagram of a memory system, in accordance with variousembodiments.

DETAILED DESCRIPTION

The following detailed description illustrates a few exemplaryembodiments in further detail to enable one of skill in the art topractice such embodiments. The described examples are provided forillustrative purposes and are not intended to limit the scope of theinvention. In the following description, for the purposes ofexplanation, numerous specific details are set forth in order to providea thorough understanding of the described embodiments. It will beapparent to one skilled in the art, however, that other embodiments ofthe present invention may be practiced without some of these specificdetails.

Several embodiments are described herein, and while various features areascribed to different embodiments, it should be appreciated that thefeatures described with respect to one embodiment may be incorporatedwith other embodiments as well. By the same token, however, no singlefeature or features of any described embodiment should be consideredessential to every embodiment of the invention, as other embodiments ofthe invention may omit such features.

Unless otherwise indicated, all numbers herein used to expressquantities, dimensions, and so forth, should be understood as beingmodified in all instances by the term “about.” In this application, theuse of the singular includes the plural unless specifically statedotherwise, and use of the terms “and” and “or” means “and/or” unlessotherwise indicated. Moreover, the use of the term “including,” as wellas other forms, such as “includes” and “included,” should be considerednon-exclusive. Also, terms such as “element” or “component” encompassboth element and components comprising one unit and elements andcomponents that comprise more than one unit, unless specifically statedotherwise.

FIGS. 1A, 1B, and 1C illustrate a schematic block diagram of memorydevices 100A, 100B, 100C according to various embodiments. Generallyspeaking, FIG. 1A illustrates embodiments of the memory device 100A thatprovide a power saving self-refresh (PSSR) operability through the useof a continuous self-refresh timer. Power saving self-refresh utilizes acontinuous self-refresh timer to reduce excess power consumption causedby unnecessary refresh operations when quickly entering and editingself-refresh mode repeatedly. FIG. 1B illustrates embodiments of thememory device 100B provide a way to implement subarray parallel refreshoperations through the use of a continuous self-refresh timer. Subarrayparallel refreshes take advantage of independent control architecturefor subarrays within a bank. This allows subarrays within a bank to beaccessed and/or refreshed independently. For example, when one of thesubarrays within the bank is being accessed, the other subarrays may berefreshed concurrently. This may be referred to as a “hidden refresh.”Various embodiments also ease scheduling and tracking requirements onmemory controllers for refreshes performed on individual subarrays.Further embodiments may implement PSSR in combination with the subarrayparallel refresh operability.

Accordingly, with reference to FIGS. 1A, 1B, and 1C, the memory device100A, 100B, 100C includes input/output pads 105, shared control logic110, temperature sensor 115, refresh control circuit 120,address/control bus 125, memory bank 0 130A, bank 1 130B, bank 2 130C,bank 3 130D (collectively “banks 130”), bank control logic 135A-D(collectively 135), and memory arrays 145A-H (collectively 145). InFIGS. 1B and 1C, in addition to these elements, the memory device 100Bmay further include subarray refresh circuits 140A-H (collectively 140)for each memory array 145, respectively. In various embodiments, refreshcontrol circuit 120 may be configured to generate a signal, “sref-tREFI”or alternatively labeled “sref_tREFI,” periodically. In someembodiments, the refresh control circuit 120 may include refreshcircuitry for generating refresh commands internally, without requiringinput from an external memory controller. In further embodiments, therefresh control circuit 120 may be configured to execute externallygenerated refresh commands.

In various embodiments, the refresh control circuit 120 may also includea self-refresh timer that, after initialization, runs continuously. Insome embodiments, the self-refresh timer may be provided outside of therefresh control circuit and coupled to the refresh control circuit 120.In various embodiments, the self-refresh timer may continue to operatewhile the bank control logic 135 performs other operations (e.g. anactivation, a read operation and a write operation) on the bank 130. Theself-refresh timer may then generate sref-tREFI each time a self-refreshrefresh time interval elapses. In various embodiments, the self-refreshtime interval may be an average minimum retention time for a particularmemory device 100, while in self-refresh mode. That is, sref-tREFIindicates when a refresh should be performed if all refreshes wereevenly spaced across each row of an individual bank, for a rank-levelrefresh. For example, in one embodiment, minimum retention time may be64 ms/8192 rows, or approximate 7.8 μs. The average minimum retentiontime, however, is temperature dependent due to leakage within the cells.Typically, the higher the operating temperature, the shorter the minimumretention time, and vice versa, the lower the operating temperature, thelonger the minimum retention time. Thus, in one set of embodiments, oneexample of the self-refresh refresh time interval may be range between1.7 μs at temperatures above 106 C and 39.7 μs at temperatures below 26C. Accordingly, in various embodiments, the self-refresh timer maygenerate sref-tREFI according to the self-refresh refresh time interval,based on temperature information received from the temperature sensor115, and indicative of a temperature, on-die or ambient, sensed by thetemperature sensor 115. In some embodiments, the self-refresh timer maybe a timer, counter, clock, or any other suitable device for determiningwhen a self-refresh refresh interval has elapsed. The self-refresh timermay further be independent of entry into or exit from self-refresh mode.For example, in some embodiments, initialization of the self-refreshtimer may not depend on, or be based on, either entry into or exit fromself-refresh mode. Furthermore, the self-refresh timer may be configuredto be neither reset nor suspended upon entry into or exit fromself-refresh mode. In various embodiments, the refresh control circuit120 may further be communicatively coupled to address control bus 125,such that the self-refresh timer may broadcast sref-tREFI to each bankcontrol logic 135 via the address/control bus 125.

In various embodiments, a rank of memory device 100 may include fourbanks. Bank 0 130A, Bank 1 130B, Bank 2 130C, and Bank 3 130D. Each ofthe banks 130 may, themselves, comprise at least two subarrays. Forexample, Bank 0 130A may include two subarrays, memory array 145A andmemory array 145B. Similarly, Bank 1 130B may include two subarrays,memory array 145C and memory array 145D. Bank 2 130C and Bank 3 130D mayeach similarly include two subarrays respectively. In variousembodiments, each subarray pair of memory arrays 145, within the samebank 130, may share a common column select logic, while havingindividual row select logic. Each bank 130 may further includerespective bank control logic 135. Each bank control logic 135 may, inturn, include subarray refresh circuits 140, referred to as “half bankrefresh circuits” in some embodiments, for each memory array 145 of thebank 130, respectively. For example, Bank 0 130A may include a bankcontrol logic 135A, the bank control logic having a subarray refreshcircuit 140A in communication with memory array 145A, and a subarrayrefresh circuit 140B in communication with memory array 145B.

FIG. 1C illustrates an alternative architecture for the memory arrays145, where the shared column select logic may be located at an edge ofthe memory arrays 145, and respective pairs of memory arrays 145 may beadjacent to each other. For example, in memory device 100C, the columnselect logic may be provided at the bottom edge of memory array 145B.Accordingly, memory array 145A and memory array 145B may be adjacent toeach other. In some embodiments, as depicted, the memory arrays mayfurther share a circuit, such as sense amplifier 155. Accordingly, a row150 of memory array 145A may share sense amp 155 with adjacent row 160of memory army 145B. This configuration may further be implemented ineach of the banks 130.

According to various embodiments, each of the subarray refresh circuits140 may include a respective refresh status counter. The subarrayrefresh circuits 140 may be configured to increment the refresh statuscounter each time the sref-tREFI signal is received, and decrement therefresh status counter each time a refresh operation is performed on acorresponding memory array 145. In some embodiments, the refresh statuscounter may be initialized with a starting value between a highthreshold—corresponding to the maximum refresh debit allowable for thesubarray, and a low threshold—corresponding to the maximum refreshcredit allowed for the subarray. The size of the refresh status countermay be selected based on the difference between the desired maximumrefresh credit and the maximum refresh debit. For example, in one set ofembodiments, the refresh status counter may be a 5-bit counter,corresponding to a maximum debit of 8 refreshes and a maximum credit of9 refreshes. In this example, the refresh status counter may beinitialized to a starting value of 9, with the maximum refresh debitcorresponding to a value of 17, and a maximum refresh creditcorresponding to a value of 0.

Continuing with the previous example, each time an sref-tREFI signal isreceived from the self-refresh timer, the status may increment by 1count. For example, after initialization, if no refreshes are madebefore sref-tREFI is received, the counter will increment from a valueof 9 to a value of 10. Thus, the refresh status counter will track thenumber of refreshes each subarray (e.g. half bank) should haveperformed, as indicated by the number of times the self-refresh refreshtime interval has elapsed. Correspondingly, each time a refreshoperation is performed on the subarray, the refresh status counter willdecrement until a low threshold is reached.

In further embodiments, each subarray refresh circuit 140 may beconfigured to perform hidden refreshes. That is, each time anothersubarray 145 on the same bank 130 is activated, the subarray refreshcircuit 140 will perform a refresh on its respective subarray 145. Forexample, if subarray refresh circuit 140A is issued an activate command,thereby activating memory array 145A, the subarray refresh circuit 140Bmay perform a refresh on memory array 145B. Similarly, with rolesreversed, if memory array 145B is activated, the subarray refreshcircuit 140A may perform a refresh on memory array 145A. Each of theother banks 130B, 130C, 130D may be configured similarly to refresh andactivate respective subarray pairs 145C-H concurrently via therespective subarray refresh circuits 140C-H. Accordingly, when a hiddenrefresh is performed, the refresh status counter for the activatedsubarray is not decremented, while the refresh status counter for thesubarray that is given a hidden refresh is decremented. In this way,subarray parallel refresh operations may be supported and tracked by therespective subarray refresh circuits 140 instead of requiring anexternal memory controller to perform these operations. However, when arefresh status counter reaches the high threshold on any of the subarrayrefresh circuits 140, the respective subarray refresh circuit 140 may beconfigured to raise a refresh alert. In some embodiments, the refreshalert may be transmitted by the subarray refresh circuit 140 to a memorycontroller requesting a refresh command to be issued. In otherembodiments, the refresh alert may be provided to the shared controllogic 110 or refresh control circuit 120, requesting an internallygenerated refresh command. Conversely, when a refresh status counterreadies the low threshold, the subarray refresh circuit 140 may beconfigured to ignore refresh commands or hidden refreshes. For example,if the refresh status counter for subarray refresh circuit 140B hasreached the low threshold, and subarray 145A has been activated, thesubarray refresh circuit 140B may block a hidden refresh from beingperformed. Similarly, if a refresh command is supplied while the refreshstatus counter is at the low threshold, the subarray refresh circuit140B may block the refresh command from being executed. The directionsof change (e.g. incrementing and decrementing) of the refresh statuscounter are not limited to the example set forth above. Similarly, thethresholds (e.g. the high threshold and the low threshold) fortriggering a refresh and blocking a refresh are not limited to theexample set forth above. For example, one skilled in the art willrecognize that the roles of high and low thresholds, as well asincrement and decrement events, may be reversed without departing fromthe scope of the method.

In various embodiments, each subarray refresh circuit 140 may furtherinclude a respective refresh address counter. The refresh addresscounters may be configured to indicate a row address of a row within thesubarray 145 to be refreshed. Accordingly, each time a refresh isperformed on the subarray 145, the refresh address counter isincremented to the next row address needing to be refreshed. In variousembodiments, the subarray refresh circuits 140 may further be configuredto block refreshes from occurring in a respective subarray 145 when therow activated in another subarray 145 on the same bank 130 is within thesection adjacent to the respective subarray 145. For example, in oneembodiment, with reference to FIG. 1C, when row 160 of the memory array145B is activated, concurrent refreshing of row 150 of memory array 145Amay be blocked by subarray refresh circuit 140A. In further embodiments,if the row address in the refresh address counter is determined to bewithin an adjacent section, the subarray refresh circuit 140 may beconfigured to perform a refresh at a different row address withoutdecrementing the refresh status counter. The subarray refresh circuit140 may then refresh the row address at the refresh address counter on asubsequent hidden refresh or refresh command.

In yet further embodiments, the bank control logic 135 may be configuredto operate in PSSR mode. In particular, embodiments of memory devices100A, 100B, and 100C may be configured to operate in a PSSR mode. Forexample, in some embodiments, bank control logic 135 mas be configuredto set a refresh flag in response to receiving the sref-tREFI signal.Alternatively, in other embodiments, the refresh flag may be set, uponreceiving sref-tREFI, at the subarray refresh circuits 140, or at therefresh control circuit 120. Upon entry into self-refresh mode, the bankcontrol logic 140 may be configured to first determine whether therefresh flag has been set. If the refresh flag has been set, the bankcontrol logic 135 may be configured to perform a refresh across theentire bank 130. However, if the refresh flag has not been set, the bankcontrol logic 135 may be configured to wait until the next sref-tREFIsignal from the self-refresh timer is received, thereby setting therefresh flag. Thus, sref-tREFI may be generated by the self-refreshtimer independent of entry into or exit from self-refresh mode. In oneset of embodiments, this may include the self-refresh timer notresetting upon entry or exit from self-refresh mode. In this way,sref-tREFI may be generated consistently, at each self-refresh refreshtime interval, as measure from the previous time that sref-tREFI wasissued. Thus, the self-refresh timer does not restart or assertsref-tREFI based on entering or exiting self-refresh mode.

Accordingly, in various embodiments, bank-level, or alternativelyrank-level, self-refreshes are only performed when both the refresh flagis set and self-refresh mode has been entered. Upon the performance of aself-refresh, the bank control logic 135 may be configured to clear therefresh flag until the next sref-tREFI is received. In this manner,excess self-refreshing from repeated entry into and exit fromself-refresh mode may be avoided. In some further embodiments, bankcontrol logic 135 may be configured to execute multiple self-refreshesupon entry into self-refresh mode. In one set of embodiments,self-refreshes may be executed until all refresh status counters in eachof the subarray refresh circuits 140 has reached a pre-determined countvalue. The pre-determined value, for example, may be the initializationvalue. In other embodiments, the pre-determined value may be the lowthreshold, or another value below the high threshold.

FIG. 2 illustrates a schematic diagram of a subarray refresh circuit 200according to various embodiments. As described above with reference tothe subarray refresh circuits 140 in FIG. 1, subarray refresh circuit200 may be configured to implement subarray parallel refresh operations,such as a hidden refresh, based on sref-tREFI. Accordingly, the subarrayrefresh circuit 200 includes a OR gate 205, NOR gate 210, AND gate 215,refresh address counter 220, refresh status counter 225, firstmultiplexer (mux) 230, second mux 235, activation address latch 240,sampling logic 245, row timing logic 250, row hammer address storage255, and adjacent address calculator logic 260.

In operation, the first OR gate 205 may be configured to indicate ifeither a complementary subarray has been activated, or if a refreshcommand has been issued. For example, the OR gate 205 may receive afirst input indicative of the activation of a complementary subarray,referred to here as an other half activate signal, and a second inputindicative of a refresh command. Accordingly, if either a complementarysubarray is active, or a refresh command is issued, the OR gate isconfigured to output true. The NOR gate 210 may be configured to block arefresh command if either an adjacent section in another subarray isbeing activated or if a low threshold of the refresh status counter 225has been reached. Accordingly, if either inputs are true, the NOR gate210 outputs a false. AND gate 215 receives outputs from both the OR gate205 and NOR gate 210. The output of the AND gate 215 is then provided tothe refresh address counter 220, the decrement pin of the refresh statuscounter 225, and as an input to row timing logic 250. Thus, if theoutput of the AND gate 215 is true, it causes a refresh status counter225 to decrement corresponding to the refresh operation. Row timinglogic 250 may be configured to provide appropriate row timings forexecuting a refresh command.

In various embodiments, the refresh address counter 220 may beconfigured to output a row address of the next row of the subarray to berefreshed. Accordingly, if the AND gate 215 provides a true output, therefresh address counter 220 may be configured to provide the row addressto the first mux 230. In some embodiments, refresh address counter 220may be configured to increment to a subsequent row address after arefresh operation has been performed, or alternatively, after providingthe row address to mux 230. First mux 230 may be configured to selectbetween a row address provided by the refresh address counter 220 and arow address provided by adjacent address calculator logic 260.Accordingly, if a row address is to be provided by the refresh addresscounter 220, the row address from refresh address counter 220 may beselected. If the next refresh cycle is scheduled as a row hammer repair(RHR) cycle, the row address from the adjacent address calculator logic260 may be selected. Second mux 235 is configured to select between arow activation address when the subarray associated with the subarrayrefresh circuit 200 is issued an activate command, and the refresh rowaddress provided by the first mux 230.

According to various embodiments, if an activate command is issued tothe subarray associated with the subarray refresh circuit 200, thesecond multiplexer 235 may transmit the row activation address to theactivation address latch 240, which then forwards the address to theappropriate row selection logic for the associated subarray. A controlsignal indicative of the activation of the associated subarray, referredto here as “this half activate,” may also be asserted as part of theactivate command. The row timing logic 250, may thus utilize “this halfactivate” to provide the correct row timings for executing the activatecommand. Sampling logic 245 may be configured to cause row hammeraddress storage 255 to store the row address at the activation addresslatch 240. For example, in some embodiments, the row hammer addressstorage 255 may itself be a latch. Adjacent address calculator logic 260may then be configured to retrieve the stored row address from the rowhammer address storage 255 to calculate the address of the adjacent rowor rows to receive row hammer repair (RHR), and provide first mux 230with an alternative row. The adjacent address calculator logic 260 maybe configured to output a row address that is adjacent to a hammeredrow. Adjacent addresses may include, without limitation, row addressesadjacent to the row address in row hammer address storage 255, rowaddresses adjacent to the immediately adjacent row addresses, or a rangeof row addresses in proximity to the row address in row hammer storage255. In some embodiments, when an adjacent row address from adjacentaddress calculator logic 260 is refreshed, it may be referred to as arefresh “steal.” A refresh “steal” does not cause a decrement to therefresh status counter 225, and may allow the row address at refreshaddress counter 220 to be refreshed on a subsequent hidden refresh orrefresh command.

FIG. 3 illustrates a timing diagram 300 for PSSR operation, according tovarious embodiments. The timing diagram 300 includes sref-tREFI 305,sref mode 310, refresh cycle 315, and refresh flag 320. Sref-tREFI 305depicts the sref-tREFI signal being asserted periodically at aself-refresh refresh time interval at rising edges 330, 335, 340, 345.Accordingly, in one example of PSSR operation, when sref-tREFI 305 isfirst asserted, the refresh flag 320 is raised. However, as depicted insref mode 310 and refresh cycle 315, a refresh is not performed untilself-refresh mode is entered at rising edge 325. Thus, rising edge 325corresponds to the rising edge of refresh cycle 315, offset by somedelay. Once the refresh is performed, the refresh flag is cleared, andreturns low. At rising edge 330 of sref-tREFI 305, the refresh flag 320is raised. Because self-refresh mode 310 is still active when therefresh flag 320 is set, refresh cycle 315 shows that a refresh isperformed immediately with the refresh flag 320. When the refresh cycleis complete, the refresh flag is once again cleared. Sref mode 310 thenshows that self-refresh mode is exited, then re-entered, betweensref-tREFI cycles. Again, because no refresh flag was set, mere exit andre-entry into self-refresh mode does not trigger a refresh. Instead, asshown at rising edge 340, refresh is only performed when both inself-refresh mode and the refresh flag is set. Continuing with thisexample, at rising edge 345, when sref-tREFI 305 is asserted afterself-refresh mode has been exited, the refresh flag 320 is set, but norefresh performed until self-refresh mode is entered into again.Accordingly, by utilizing a continuous self-refresh timer to generatesref-tREFI, memory may repeatedly enter and exit self-refresh mode,multiple times per sref-tREFI interval, without performing a refreshoperation each time self-refresh mode is re-entered.

FIG. 4 is a timing diagram 400 showing an example of subarray parallelrefresh operation according to various embodiments. The example timingdiagram 400 includes a sref-tREFI 405, half-A activate 410, half-Arefresh 415, refresh status count A 420, half-B activate 425, half-Brefresh 430, refresh status count B 435, and refresh alert 440.Sref-tREFI 405 illustrates the sref-tREFI signal, as periodically raisedat a self-refresh refresh time interval. Half-A activate 410 isindicative of the activation of subarray half-A over time. Half-Arefresh 415 depicts refreshes of subarray half-A over time. Refreshstatus count A 420 shows the count value of a refresh status counter forsubarray half-A. Correspondingly, half-B activate 425 illustratesactivation of subarray half-B, and half-B refresh 430 illustratesrefreshes performed on subarray half-B. Refresh status count B 435 showsthe count value of a refresh status counter for subarray half-B, andrefresh alert 440 depicts whether an alert has been raised based on arefresh status count exceeding a high threshold. In various embodiments,subarray half-A may belong to the same bank as subarray half-B, thusbeing complementary subarrays.

As depicted in the example, subarray half-A is repeatedly activated forthe first two sref-tREFI intervals, a total of 8 times, without beingrefreshed. Sref-tREFI 405 has been asserted twice during that interval.Refresh status count A 420 may have started at a value of 14, indicatinga refresh debit of five refreshes. At each sref-tREFI 405 the refreshstatus counter A 420 is incremented. Thus, refresh status count A 425has a value of 16 at the end of the second sref-tREFI interval. Duringthis same time interval, subarray half-B has not been activated, asshown by half-B activate 425. Instead, as shown in half-B refresh 430,subarray half-B is refreshed in parallel with the half-A activate 410,via hidden refresh. Accordingly, refresh status count B 435, which had astarting value of 8, may be incremented by the first sref-tREFI 405, butdecrements by 1 for each hidden refresh. The second sref-tREFI 405increments the refresh status count B 435 to 6, but is again decrementedby 1 for each hidden refresh, ending with a value of two at the end ofthe second sref-tREFI interval. The third sref-tREFI 405 may incrementrefresh status count A 420 to a high threshold corresponding, in thisexample, to a value of 17. Accordingly, a refresh alert 440 may beraised, and a refresh command requested from the memory controller. Oncethe refresh command is received, a refresh may be performed globallyacross the entire bank, as shown in both half-A refresh 415 and half-Brefresh 430. Thus, when subarray half-A refreshes, the refresh statuscount A is decremented from a value of 17 to a value of 16. Similarly,refresh status count B 435 is decremented from a value of 3 to a valueof 2. At the end of the third sref-tREFI interval, subarray half-A isactivated two more times, causing two hidden refreshes of subarrayhalf-B. Refresh status count B 435 is then decremented from a value of 2to a low threshold corresponding, in this example, to a value of 0 atthe end of the third sref-tREFI interval. The fourth sref-tREFI 405against causes a refresh alert 440 to be raised, and another refreshcommand to be issued. Refresh status count B 435, although being at thelow threshold, is incremented by the fourth sref-tREFI 405, allowingsubarray half-B to be refreshed again, by the refresh command, whichthen returns the refresh status count B to 0. Towards the end of thefourth sref-tREFI interval, subarray half-A is again activated twice.This time, because refresh status count B 435 is at the low threshold,no hidden refreshes are performed on subarray half-B. This pattern isthen repeated for the fifth sref-tREFI 405, over a fifth sref-tREFIinterval, with one refresh executed on both subarrays half-A and half-B,corresponding to the refresh alert 440, and subsequent hidden refreshesof subarray half-B being blocked.

It is to be understood that the above examples provided in FIGS. 3 & 4are simplified timing diagrams to aid in the conceptual understanding ofPSSR and subarray parallel refresh operation. Therefore, the embodimentsillustrated in FIGS. 3 & 4 should not be taken as limiting in any way.

FIGS. 5A & 5B are flow diagrams of a process for PSSR operation,according to various embodiments. FIG. 5A illustrates a method 500A ofoperating a self-refresh timer, in accordance with various embodiments.The method 500A begins, at block 505, by generating timer data. Asdiscussed with respect to the previous embodiments, the self-refreshtimer may generate timer data continuously, upon initialization, andindependent of entry into or exit from self-refresh mode. The method500A may continue, at decision block 510, by determining, via theself-refresh timer, whether a self-refresh refresh time interval haselapsed and sref-tREFI has been asserted. As described with respect tothe embodiments above, the self-refresh time interval may correspond toan average minimum retention time for the memory device, at a giventemperature, while in self-refresh mode. If, a self-refresh refresh timeinterval has elapsed, the self-refresh timer may assert the sref-tREFIsignal. If sref-tREFI has been asserted, at block 515, a refresh flagmay be set. If sref-tREFI has not yet been asserted, the self-refreshtimer may continue wait until the self-refresh refresh time interval haselapsed before issuing sref-tREFI. In various embodiments, the refreshflag may be set by the self-refresh timer or in various refresh controlcircuits. For example, in some embodiments, the refresh flag may be setat a refresh control circuit at a rank-level, bank-level, orsubarray-level. Accordingly, with reference to FIG. 1A & 1B, the refreshcontrol circuit may be part of any of the internal, shared refreshcontrol circuit 120 for one or more banks, bank control logic 135 forindividual banks, or in subarray refresh circuits 140.

FIG. 5B illustrates a method 500B for PSSR operation, according tovarious embodiments. The method 500B begins, at block 550, at an idlestate until, at block 520, a self-refresh mode command is received. Whenshe self refresh mode command is received, a refresh control circuit,such as, without limitation, the subarray refresh circuit, bank controllogic, or a shared internal refresh control circuit may enter intoself-refresh mode. Accordingly, in various embodiments, the refreshcontrol circuit may be a refresh control circuit at any of a rank level,bank level, or a subarray level. Then, at decision block 525, therefresh control circuit determines whether the refresh flag has beenset. If the refresh flag has not been set, at block 530, the refreshcontrol circuit may wait until the refresh flag is set. Otherwise, atblock 545, when a self-refresh exit command is received, the refreshcontrol circuit may exit from self-refresh mode and return to an idlestate, at block 550. If, at decision block 525, a refresh flag has beenset, a refresh is performed, at block 535, via the refresh controlcircuit. After the refresh has been performed, at block 540, the refreshflag is cleared and the refresh control circuit enters a waiting state,at block 530.

FIGS. 6A & 6B are flow diagrams of a subarray parallel refreshoperation. FIG. 6A is a flow diagram of a method 600A of operating aself-refresh timer, in accordance with various embodiments. As in FIG5A, the method 600A begins, at block 605, by generating timer data. Theself-refresh timer may generate timer data continuously, afterinitialization, and independent of entry into or exit from self-refreshmode. The method 600A may continue, at decision block 610, bydetermining, via the self-refresh timer, whether a self-refresh refreshtime interval has elapsed and sref-tREFI has been asserted. If, aself-refresh refresh time interval has elapsed, the self-refresh timermay assert the sref-tREFI signal. If sref-tREFI has been asserted, atblock 615, a the refresh status counter may be incremented. Ifsref-tREFI has not yet been asserted, the self-refresh timer maycontinue wait until the self-refresh refresh time interval has elapsedbefore issuing sref-tREFI.

FIG. 6B illustrates a method 600B for subarray parallel refresh of amemory device, in accordance with various embodiments. The methodbegins, at decision block 620, by determining whether any refresh statuscounters for any of the subarrays reaches a high threshold. In theillustrated embodiments, the high threshold may correspond to a countervalue of 17, or a refresh status count that exceeds 16. In otherexamples, as described above, other values may be established for thehigh threshold, as well as a low threshold and an initialization value.In various embodiments, individual subarray refresh circuits,respectively associated with each subarray, may make their respectivedeterminations.

If the high threshold has been reached by any of the subarray refreshcircuits, at block 625, a refresh alert may be raised to a memorycontroller, requesting that a refresh command be issued. In someembodiments, the refresh command may be a global refresh command acrossone or more ranks, a per-bank refresh command, or a refresh command fora subset of banks in one or more ranks. If no refresh status countreaches the high threshold, the subarray refresh circuits may enter intoan idle state, at block 630.

At block 635, an activate command may be received for subarray half-A.In various embodiments, a bank may include one or more subarrays,including subarrays half-A and half-B. In response to receiving theactivate command, the subarray refresh circuit for subarray half-A mayactivate subarray half-A. At decision block 640, the subarray refreshcircuit for subarray half-B may determine whether the refresh statuscount for subarray half-B has reached the low threshold. In this case,the low threshold may correspond to a value of 0. If the refresh statuscount for the subarray half-B has reached the low threshold, no hiddenrefresh is performed, and resumes, at decision block 620, to determinewhether any refresh status counts have exceeded the high threshold.However, if the refresh status count for subarray half-B has not reachedthe low threshold, at block 645, a hidden refresh of subarray half-B maybe performed concurrently with the activation of subarray half-A. Oncethe hidden refresh has been performed, at block 650, the refresh statuscount for subarray half-B may be decremented, at the refresh statuscounter for subarray half-B, and the subarray refresh circuits return toan idle state, at block 630, if no refresh status counters for anysubarrays have reached the high threshold.

At block 655, an activate command may be received for subarray half-B.In response to receiving the activate command, the subarray refreshcircuit for subarray half-B may activate subarray half-B. At decisionblock 660, the subarray refresh circuit for subarray half-A maydetermine whether the refresh status count for subarray half-A hasreached the low threshold, in this case 0. If the refresh status countfor subarray half-A is at the low threshold, no hidden refresh may beperformed, and proceeds, at decision block 620, to check whether anyother refresh status counts have exceeded the high threshold. However,if the refresh status count for subarray half-A has not reached the lowthreshold, at block 670, a hidden refresh of subarray half-A may beperformed concurrently with the activation of subarray half-B. Once thehidden refresh has been performed, at block 675, the refresh statuscount for subarray half-A may be decremented, via the refresh statuscounter for subarray half-A, and the subarray refresh circuits mayreturn to an idle state, at block 630, if no refresh status counters forany subarrays have reached the high threshold.

At block 685, a refresh command may be received from a memorycontroller. Upon receiving the refresh command, the respective subarrayrefresh circuits may determine whether the respective refresh statuscounts for subarrays half-A and half-B are at a low threshold. Asbefore, if the refresh status counts for the subarrays are above the lowthreshold, refreshes of the respective subarrays may be performed. Ifthe refresh status counts are at the low threshold, the refresh commandmay be ignored.

FIG. 7 is a block diagram of a portion of a memory system 700, inaccordance with various embodiments. The system 700 includes an array702 of memory cells, winch may be, for example, volatile memory cells(e.g., dynamic random-access memory (DRAM) memory cells, low-power DRAMmemory (LPDRAM), static random-access memory (SRAM) memory cells),non-volatile memory cells (e.g., flash memory cells), or other types ofmemory cells. The memory 700 includes a command decoder 706 that mayreceive memory commands through a command bus 708 and provide (e.g.,generate) corresponding control signals within the memory 700 to carryout various memory operations. Fur example, the command decoder 706 mayrespond to memory commands provided to the command bus 708 to performvarious operations on the memory array 702. In particular, the commanddecoder 706 may be used to provide internal control signals to read datafrom and write data to the memory array 702. Row and column addresssignals may be provided (e.g., applied) to an address latch 710 in thememory 700 through an address bus 720. The address latch 710 may thenprovide (e.g., output) a separate column address and a separate rowaddress.

The address latch 710 may provide row and column addresses to a rowaddress decoder 722 and a column address decoder 728, respectively. Thecolumn address decoder 728 may select bit lines extending through thearray 702 corresponding to respective column addresses. The row addressdecoder 722 may be connected to a word line driver 724 that activatesrespective rows of memory cells in the array 702 corresponding to thereceived row addresses. The selected data line (e.g., a bit line or bitlines) corresponding to a received column address may be coupled to aread/write circuitry 730 to provide read data to an output data buffer734 via an input-output data path 740. Write data may be provided to thememory array 702 through an input data buffer 744 and the memory arrayread/write circuitry 730.

Temperature sensor 716 may be an on-die temperature sensor configured tomeasure a temperature, and provide temperature information, TEMP, forexample, to other circuits of the memory 700, such as refresh controllogic 712. In various embodiments, refresh control logic 712 includes aself-refresh timer as described in the above embodiments. Theself-refresh timer may run continuously after initialization, andindependently of entry into or exit from self-refresh mode. Theself-refresh timer may further be configured to generate sref-tREFIperiodically, each time a self-refresh refresh time interval elapses.Memory 700 may further include bank control circuits 714. Bank controlcircuits 714 may include subarray refresh circuits for individualsubarrays of each bank. The bank control circuits 714 and refreshcontrol logic 712, may be configured to provide both PSSR and subarrayparallel refresh capabilities, in accordance with the previouslydescribed embodiments.

While certain features and aspects have been described with respect toexemplary embodiments, one skilled in the art will recognize thatvarious modifications and additions can be made to the embodimentsdiscussed without departing from the scope of the invention. Althoughthe embodiments described above refer to particular features, the scopeof this invention also includes embodiments having different combinationof features and embodiments that do not include all of the abovedescribed features. For example, the methods and processes describedherein may be implemented using hardware components, softwarecomponents, and/or any combination thereof. Further, while variousmethods and processes described herein may be described with respect toparticular structural and/or functional components for ease ofdescription, methods provided by various embodiments are not limited toany particular structural and/or functional architecture, but insteadcan be implemented on any suitable hardware, firmware, and/or softwareconfiguration. Similarly, while certain functionality is ascribed tocertain system components, unless the context dictates otherwise, thisfunctionality can be distributed among various other system componentsin accordance with the several embodiments.

Moreover, while the procedures of the methods and processes describedherein are described in a particular order for ease of description,various procedures may be reordered, added, and/or omitted in accordancewith various embodiments. The procedures described with respect to onemethod or process may be incorporated within other described methods orprocesses; likewise, hardware components described according to aparticular structural architecture and or with respect to one system maybe organized in alternative structural architectures and or incorporatedwithin other described systems. Hence, while various embodiments aredescribed with or without certain features for ease of description, thevarious components and/or features described herein with respect to aparticular embodiment can be combined, substituted, added, and/orsubtracted from among other described embodiments. Consequently,although several exemplary embodiments are described above, it will beappreciated that the invention is intended to cover all modificationsand equivalents within the scope of the following claims.

1. An apparatus comprising: a self-refresh timer configured to generatea signal periodically, wherein a period of the signal is based on aself-refresh refresh time interval, wherein the self-refresh refreshtime interval is dependent, at least in part, on temperatureinformation; a memory bank comprising at least a first subarray; a firstsubarray refresh circuit communicatively coupled to the first subarrayand comprising a first refresh status counter; wherein the firstsubarray refresh circuit is configured to: receive the signal from theself-refresh timer; change a count value of the first refresh statuscounter in a first direction each time the signal is received; andchange the count value of the first refresh status counter in a seconddirection each time the first subarray is refreshed; and wherein thefirst subarray refresh circuit is further configured to set a refreshflag upon receiving the signal, wherein in self-refresh mode, the firstsubarray refresh circuit is further configured to: determine whether therefresh flag is set; refresh the first subarray if the refresh flag isset; and clear the refresh flag in response to performing the refresh.2. The apparatus of claim 1, wherein generation of the signal isindependent of entry or exit of self-refresh mode.
 3. The apparatus ofclaim 1, further comprising a second subarray, and wherein the firstsubarray refresh circuit is further configured to refresh the firstsubarray when the second subarray is activated.
 4. The apparatus ofclaim 1, wherein the first subarray refresh circuit is furtherconfigured to determine whether the first refresh status counter hasreached a first threshold, wherein if the first threshold has beenreached, the first subarray refresh circuit is configured to request arefresh command from a memory controller.
 5. The apparatus of claim 1,wherein the first subarray refresh circuit is further configured todetermine whether the first refresh status counter has reached a secondthreshold, wherein if the second threshold has been reached, the firstsubarray refresh circuit is configured to block refresh of the firstsubarray.
 6. The apparatus of claim 1, wherein the first subarrayrefresh circuit further comprises a refresh address counter configuredto increment after every refresh of the first subarray, wherein therefresh address counter is configured to indicate a row address of thefirst subarray to be refreshed.
 7. The apparatus of claim 3, wherein thefirst subarray refresh circuit is further configured to block refresh ofthe first subarray if a row activated in the second subarray is adjacentto a row of the first subarray to be refreshed.
 8. The apparatus ofclaim 1, wherein the first subarray refresh circuit is furtherconfigured to determine whether self-refresh mode has been entered,wherein upon entry into self-refresh mode, the first subarray refreshcircuit is further configured to continually refresh the first subarrayuntil the first refresh status counter has reached a pre-determinedcount.
 9. The apparatus of claim 8, wherein, after the pre-determinedcount has been reached, the first subarray refresh circuit is configuredto refresh the first subarray in response to receiving the signal fromthe self-refresh timer.
 10. The apparatus of claim 1, further comprisinga second subarray refresh circuit communicatively coupled to a secondsubarray, and wherein the second subarray refresh circuit comprises asecond refresh status counter, wherein the second subarray refreshcircuit is further configured to: receive the signal from theself-refresh timer; change a count value of the second refresh statuscounter in the first direction each time the signal is received; andchange the count value of the second refresh status counter in thesecond direction each time the second subarray is refreshed, refresh thesecond subarray when the first subarray is activated, if the secondrefresh status counter has not reached a second threshold; and blockrefresh of the second subarray if the second refresh status counter hasreached the second threshold.
 11. (canceled)
 12. An apparatuscomprising: a self-refresh timer configured to generate a refresh signalperiodically; a memory bank; and a controller coupled to theself-refresh timer and configured to receive the refresh signal from theself-refresh timer and refresh the memory bank responsive, at least inpart, to generation of the refresh signal when the apparatus is in aself-refresh mode, and wherein the self-refresh timer is furtherconfigured to generate the refresh signal periodically while theapparatus is in a first operation mode different from the self-refreshmode.
 13. The apparatus of claim 12, wherein the first operation modeincludes at least one of read and write operation.
 14. The apparatus ofclaim 12, wherein the controller is further configured to set a flagresponsive, at least in part, to generations of the refresh signal whilethe apparatus is in the first operation mode, the controller is furtherconfigured to determine whether the flag is set or not when theapparatus enters the self-refresh mode, to perform the refresh operationon the memory bank when the apparatus enters the self-refresh mode ifthe flag has been set, and to be prevented from performing the refreshoperation on the memory bank when the apparatus enters the self-refreshmode if the flag has not been set.
 15. The apparatus of claim 12,wherein the memory bank comprises first and second memory arrays thatare configured to be refreshed independently of each other, and theapparatus further comprises: first and second array control circuitscoupled respectively to the first and second memory arrays, and whereineach of the first and second array control circuits comprises a refreshstatus counter that is configured to change a count value thereof in afirst direction responsive to the refresh signal and change the countvalue thereof in a second direction responsive to performing the refreshoperation on a respective memory array.
 16. The apparatus of claim 15,wherein each of the first and second memory array control circuits isfurther configured to provide an alert signal responsive, at least inpart, to the count value of the status counter thereof reaching a firstthreshold value.
 17. The apparatus of claim 15, wherein each of thefirst and second memory array control circuits is further configured toprevent the respective memory array from being refreshed when the countvalue of the refresh status counter thereof reaches a second thresholdvalue.
 18. The apparatus of claim 15, wherein one of the first andsecond array control circuits is configured to perform the refreshoperation on the respective memory array when the other of the first andsecond array control circuits activates the respective memory array. 19.The apparatus of claim 15, wherein each of the first and second memoryarray control circuits further comprises an address counter that isconfigured to provide an address designating cells in the respectivearray to be refreshed.
 20. A system comprising: a memory controllerconfigured to provide a self-refresh entry command and a self-refreshexit command, and a memory device coupled to the memory controller andconfigured to enter a self-refresh mode responsive to the self-refreshentry command and exit the self-refresh mode responsive to theself-refresh exit command, the memory device comprising: a self-refreshtimer configured to generate a refresh signal periodically,independently of the self-refresh entry command and the self-refreshexit command; a first memory array; and a first array control circuitcoupled to the self-refresh timer and configured to generate an alertsignal responsive, at least in part, to the refresh signal, and whereinthe memory controller is further configured to provide the self-refreshentry command responsive, at least in part, to the alert signal.
 21. Thesystem of claim 20, wherein the first array control circuit comprises arefresh status counter that is configured to change a count value in afirst direction responsive to the refresh signal and the first arraycontrol circuit is configured to provide the alert signal when the countvalue reaches a first threshold value.
 22. The system of claim 21,wherein the refresh status counter is further configured to change thecount value in a second direction responsive to the first memory arraybeing refreshed.
 23. The system of claim 20, wherein the memory devicefurther comprises a second memory array that shares a selection circuitwith the first memory array and a second array control circuit, andwherein the memory controller is further configured to provide anactivate command to the second memory array, and the first array controlcircuit is further configured to refresh the first memory array whilethe second array control circuit is performing an activate operation onthe second memory array responsive to the activate command.